Generally, various advanced processes may be employed in design and fabrication of IC devices, particularly to aid with accurate integration of advanced technology components/structures having reduced geometries for higher IC devices. In scaling of FINFET devices, smaller fin pitch and shallow-trench-isolation (STI) regions/structures may be utilized. Conventional FINFET STI regions may result in poor epi junction growth for recessed source/drain (S/D) regions, which may be due to poor epitaxial material growth since the surrounding environment or sidewalls are formed of oxide. Recent improvements in STI structures (e.g., with an extra masking step) may allow implementation of a “mushroom-top” STI structure with one STI in between adjacent FINFET portions (i.e., an SDB). In this approach, the S/D regions, after S/D recess etching, may still preserve some “Si-seeding” on the sidewall (near the STI structure) for better S/D epi formation. However, the “mushroom-top” of the STI structure is sensitive to alignment errors (e.g., overlay+/−6 nm) and difficult to scale to smaller technology nodes (e.g., 10 nm, 7 nm, etc.) causing transistor performance variations (related to the epi volume variations at S/D).
FIGS. 1A and 1B illustrate example FINFET IC devices. FIG. 1A illustrates an example FINFET IC device that includes Si fin 101, gate electrodes 103 and 105 for two FINFETs, S/D regions 107/109, STI region 111, and a gate electrode 113 (e.g., dummy gate) on the STI region. As illustrated, there is poor growth in portions 115/117 of the epitaxially grown material in the S/D regions 107/109, as the surrounding environment is oxide for epitaxy growth. Also, there is poor isolation between the S/D junctions and the gate 113. Adverting to FIG. 1B, another example FINFET IC device includes fins 119 and 121 formed from a semiconductor substrate 101, a non-recessed STI region 123 disposed between the fins 119 and 121, a dummy gate 125 disposed on the non-recessed STI region 123, and active gates 127 and 129. The process utilized in forming the S/D regions between STI 123 and each of gates 127 and 129 is sensitive to alignment errors as the total amount of epi growth at S/D is related to the alignment, impacting the stress level at S/D and device performance; thus, additional layout area of S/D is needed. Other similar methods for FINFET IC devices face similar issues and challenges in the semiconductor industry.
A need therefore exists for a methodology for creating self-aligned FINFET SDBs for minimum gate junction pitch and improved epitaxy formation and the resulting device.